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Canal-and-Lock System
for discrete simulators checks features for modeling complex logic, which has to be verified by deterministic datasets. Also variance reduction capabilities are checked. Download detailed definitionSolutions:
| Simulation Language | Version | Publishedin SNE | Source | |
|---|---|---|---|---|
| GPSS/H | SNE 16 p 32 | [PDF] | ||
| MicroSaint | SNE 17 p 36 | |||
| SIMUL_R | SNE 19 p 40 | |||
| Simplex II | SNE 20 p 28 | [PDF] | ||
| SLX | SNE 22 p 43 | [PDF] | ||
| CSIM | SNE 41/42 p 47 | [PDF] | ||
| Java | SNE 43 p 28 | [PDF] | ||
| MATRIXx | SNE 20 p 31 | [PDF] |